Hardware and digital design
Coursework that left the lab
FPGA Digital Systems · ENEL 453 · Sep 2026 to present
SystemVerilog designed and simulated in AMD Vivado, then synthesized, implemented and deployed to a Basys 3 (Artix-7). Timing reports drive the design: worst negative slack sets the maximum clock frequency.
RC Car on Custom PCBs · Team of 4 · Jan to May 2026
An ESP32 car with coil-based metal detection and ultrasonic navigation that found all eight course objects. I wrote the ESP-IDF firmware that pulses the detection coil, averages 200 ADC samples per reading and compares against a boot-time baseline.
BSc Electrical Engineering, Schulich School of Engineering, University of Calgary. Minors in Aerospace and Business. Expected May 2029. Available for a 16-month internship, May 2027 to Aug 2028.
Co-founder and Vice President, E.Q.O.L. (Equalities in All Qualities of Life). C, C++, Python, SQL, MATLAB, SystemVerilog.
